The flexibility and programmability of programmable logic devices such as Field Programmable Gate Arrays (FPGAs) and Complex Programmable Logic Devices (CPLDs) have made them suitable for a multitude of applications including digital signal processing blocks, local area network media access controllers, and high speed bus interfaces as examples. As the speed and performance of programmable logic devices increase, these devices have become more suitable for high speed and high performance applications. As operating speeds increase, a number of technical challenges are encountered.
A specific example of a high performance application suitable for programmable logic devices, more particularly FPGAs, is an interface to a data transfer bus such as a front-side bus (FSB). An FSB interfaces a central processing unit (CPU) to the rest of the hardware on a computer such as a chipset containing memory controllers and I/O controllers, as well as other devices and peripherals. Some interface devices and peripherals can be implemented by programmable logic devices such as FPGAs and CPLDs. As the clocking speeds of the FSB increase past 1 GHz, however, high frequency performance of the programmable logic device implementing these high speed functions become more and more critical. In particular, the performance of I/O blocks 115, which are necessary to drive the FSB, needs to maintain high performance standards, as well.
One particular type of FSB architecture is the Intel Front-Side Bus which can operate at speeds of 1066 MHz. The Intel Front-Side Bus is implemented using an open-drain transmission system that requires a 1.2V termination voltage coupled to a bus line through a termination resistor.
One of the difficulties of implementing open-drain transmission systems using programmable logic devices is that FPGA and CPLD output blocks, such as I/O block 115 shown in FIG. 1 are commonly configured to accommodate a variety of output standards. One such FPGA that incorporates multiple standards such as LVCMOS, LVTTL, HSTL, SSTL, GTL, PCI, LVDS, HT, LVPECL, BLVDS, LVDCI and HSLVDC among others is the Xilinx Virtex-4® FPGA and is described on page 8 of the Virtex-4 FPGA Data Sheet: DC and Switching Characteristics, published Jun. 6, 2008, available from Xilinx, Inc., 2100 Logic Drive, San Jose, Calif. 95124, which pages are incorporated herein by reference. (Xilinx, Inc., owner of the copyright, has no objection to copying these and other pages referenced herein but otherwise reserves all copyright rights whatsoever.) A selection of available programmable I/O standards provides programming and application flexibility. However, in order to accommodate a variety of output standards, circuitry dedicated to each standard, such as driving circuits and pull-up and pull-down resistors, resides within I/O block 115 and may be coupled to an output pad. This extra circuitry creates excess output capacitance on the I/O pad making it more challenging to drive the output pad in high-speed applications such as a 1066 MHz FSB. For example, in open-drain standards such as terminated Gunning Transceiver Logic (GTL), an increase in output capacitance at the driving pin directly affects the rise time of the logic bus, which is based on the RC time constant of the pull-up resistor and bus-capacitance. Given that a typical programmable logic IC may have an output capacitance upwards of about 5× the output capacitance of a custom logic device, a typical programmable logic IC may fail to adequately drive a high-speed open-drain bus.
To accommodate high-speed I/O driving applications in programmable logic IC's, what is needed are circuits and systems of driving high speed outputs while still maintaining flexibility in programming.